1. Field of the Invention
This invention relates to the field of semiconductor processing and MOS transistors and, more particularly, to a structure and method in which source/drain regions within the semiconductor substrate are detached or laterally displaced from the transistor gate.
2. Description of the Relevant Art
The operating characteristics of transistors fabricated with metal-oxide-semiconductor (MOS) integrated circuit techniques are a function of the transistor's dimensions. In particular, the source-to-drain current (I.sub.ds) is proportional to the ratio of is the transistor's width (W) to the transistor's length (L). For a given transistor width and a given biasing condition (e.g., V.sub.G =3V, V.sub.D =3V, and V.sub.S =0V), I.sub.ds is maximized by minimizing the transistor length L. Minimizing transistor channel length also improves the speed of integrated circuits comprised of a large number of individual transistors because the larger drain current associated with a short channel length can drive the adjoining transistors into saturation more quickly. Minimizing L is, therefore, desirable from an device operation standpoint. In addition, minimizing the transistor length L is desirable from a manufacturing perspective because a smaller area of silicon is required to manufacture a transistor having a smaller length. By minimizing the area required for a given transistor, the number of transistors available for a given area of silicon increases and with it, a corresponding increase in the circuit complexity that can be achieved on the given area of silicon.
The benefits achieved by minimizing the channel length L are accompanied by an increased sensitivity to voltage breakdown. As device channel lengths drop below 0.5 microns, the stability and reliability of the transistor must be carefully monitored. One widely recognized and easily tested parameter is the drain voltage breakdown (commonly referred to as BVDSS). BVDSS can be measured by grounding the gate, source, and substrate of a test transistor and ramping the drain voltage from 0 volts while measuring the drain voltage at which a drain current of approximately 1 .mu.A begins to conduct. BVDSS, therefore, indicates a drain voltage at which the device conducts current whether or not a bias is applied to the transistor gate. Because unwanted drain currents increase the power requirements of the integrated circuit, the temperature of the integrated circuit, and can result in an inadvertent activation of other transistors within the circuit, the maximization of BVDSS is critical, especially in short channel devices. In conventional MOS transistors, BVDSS begins to approach the operating voltage of the transistor as the channel length falls below approximately 0.5 microns. FIG. 1 shows a transistor 10 which is comprised of a substrate 12, a gate dielectric 14, a gate electrode 16, and a pair of source/drain regions 20a and 20b. Transistor 10 is fabricated such that channel boundaries 22a and 22b of source/drain regions 20a and 20b are in close proximity to lateral positions of first and second sidewalls 18a and 18b of gate electrode 16. Source/drain regions 20a and 20b are typically heavily doped with an impurity to provide a plentiful source of mobile carriers for conduction after an inversion region is created in the substrate 12 under gate electrode 16. The use of heavily doped source/drain regions that have a channel boundary coincident with sidewalls of the transistor gate results in a transistor having an undesirably low field breakdown voltage BVDSS. BVDSS decreases with channel length L partly because the maximum electric field within channel region 21 of transistor 10 increases. This increased electric field can provide sufficient energy to mobile carriers within drain region 20b to overcome the reversed biased junction between drain region 20b and channel region 21 thereby increasing the drain current.
One well known approach to reduce the short channel effects described in the preceding paragraph includes the fabrication of lightly doped drain (LDD) structures. FIG. 2 shows a typical transistor 30 incorporating LDD regions 40a and 40b. Transistor 30 includes a semiconductor substrate 32, a gate dielectric 34, a gate electrode 36, lightly doped regions 40a and 40b, and heavily doped regions 48a and 48b. Transistor 30 also includes spacer structures 44a and 44b that facilitate the lateral displacement of the heavily doped regions 48a and 48b from sidewalls 38a and 38b of gate electrode 36. Typically, the peak impurity concentration within lightly doped drain regions 40a and 40b is less than the peak impurity concentration within heavily doped regions 48a and 48b. Channel boundaries 42a and 42b of lightly doped regions 40a and 40b are approximately aligned with lateral positions of first sidewall 38a and second sidewall 38b of gate electrode 36. Interior boundaries 49a and 49b of heavily doped regions 48a and 48b are laterally displaced from sidewalls 38a and 38b of gate electrode 36. Because lightly doped regions 40a and 40b are typically doped with a lighter impurity concentration than heavily doped regions 48a and 48b, the resistivity of lightly doped regions 40a and 40b is higher than a resistivity of heavily doped regions. Accordingly, an applied drain voltage is distributed across lightly doped drain region 40b and results in reduced electric field within channel region 41 that results in an increased BVDSS of transistor 30. It will be appreciated that in the case of both transistor 10 of FIG. 1 and transistor 30 of FIG. 2, the channel boundaries of the source/drain impurity distributions are approximately coincident with sidewalls of the gate electrode. This alignment of the source/drain boundaries and the gate electrode sidewalls has generally been considered desirable. Significant overlap between the gate electrode and the source/drain regions is avoided because of the increased parasitic capacitance that results when a source/drain region extends significantly below the gate electrode. Because the transistor drain typically functions as the device output and the gate electrode typically functions as the device input, any parasitic capacitance between drain and gate produces an undesirable feedback mechanism that limits the high frequency operation of the device. See, e.g., Ben G. Streetman, Solid State Electronic Devices 319-321 (Prentice-Hall 1980). Therefore, conventional transistors have generally been fabricated in a manner designed to minimize overlap between the source/drain regions and the gate electrode, most notably through the use of the self aligned silicon gate technology. Despite the desire to minimize parasitic capacitance due to excessive overlap, conventional transistor design typically required some lateral overlap between the source/drain regions and the gate electrode. The overlap was generally considered necessary to form a complete channel from source to drain region and it was believed that a non-functional device could result if the gate did not extend to the source and drain impurity distributions. Id.
The requirement that the gate electrode extend to the source and drain impurity distributions results in an undesirably low BVDSS when the channel length of the transistor drops below 0.5 microns. This undesirable result can only be partially offset by implementation of the LDD structures described with respect to FIG. 2. The presence of lightly doped drain structures does not fully restore the BVDSS of the transistor to a desired range. (It is generally considered desirable to have BVDSS at least 1.5 to 3 times greater than the normal operating voltage of the particular technology). As discussed previously, short channel devices are desirable because of the larger number of such devices that can be fabricated within a given area. Therefore, it is highly desirable to design and fabricate a semiconductor structure and process resulting in transistors having increased tolerance to BVDSS for channel lengths well below 0.5 microns.